1. Field of the Invention
The present invention relates to an insulated structure of a chip array component and fabrication method of the same. In particular, to a chip array component whose main body is entirely and densely coated with a high resistance insulation material and then by removing parts of the coating at the positions of the terminal electrodes using sand blasting, laser trimming, grinding or etching process, so as to obtain a desired finished structure of the chip array component.
2. Description of the Prior Art
The chip array component is widely applied as an important component in many electronic products. Different types of materials are applied to form a variety of electronic elements according to their respective physical properties. For example, the ceramic dielectric substance is a suitable material for forming the chip capacitor array component, the ceramic ferrite substance is a suitable material for forming the chip bead array component, and the ceramic semiconductor substance is suitable for forming the chip varistor array component. In the materials mentioned above, although a ceramic dielectric substance with good insulation property is selected for forming a chip arrayed type capacitor element, the insulation resistance of the capacitor element is still not reliable under high voltage applications. And the chip arrayed type bead element or varistor element etc. formed of material with a lower volume resistivity also has a problem of poor insulation resistance. Even there might arise a problematic insulation resistance appealing on the surface of an element during the fabrication process.
Furthermore, in a chip array component of insufficient surface insulation resistance, it is difficult to fabricate terminal electrodes with excellent soldering property. In order to rectify such a disadvantage, a very special means and process for forming terminal electrodes with definite soldering properties should be considered. However, these two conditions have the problems of manufacturing process or quality of the product.
FIGS. 1A and 1B are two perspective views of terminal electrode of a chip array component fabricated with a conventional method. On the main body of a component 10, terminal electrodes for the chip array component are formed directly at the positions 11a, 11b, 11c, 11d, 11e, 11f, 11g and 11h with an appropriate electrode material.
In the case an ordinary conducting material is used for forming the terminal electrodes, as shown in FIG. 1B, an electroplating process will be performed to form soldering interfaces 12a˜12h at the positions on the terminal electrode conductor where the terminal electrodes 11a˜11h are to be formed at the final stage of the chip array fabrication process.
In order to reliably soldering the terminal electrodes in the chip array component with an insufficient surface insulation resistance, the prior arts encounter the following problems:
1. It is an art of directly using a conducting material containing a precious metal component to form the terminal electrode so as to meet the requirement of soldering. However, to solve the soldering problems in this art is not only increasing the production cost due to selecting the expensive conductor for fabricating terminal electrodes. Moreover, the aforesaid conducting material is easy to deteriorate by oxidation and then causing the finished product to lose its reliability and degrade its quality comparing with the soldering interface.
2. Another art usually adopted by the prior fabrication process to overcome the above defect is to utilize a specially plating solution and plating process so as to grow a preferable soldering interface at the position where the terminal electrode is to be formed. However, such a particularly designed treating method is likely incompatible with a common chip array component resulting in vainly wasting the investment and increasing an extra work for waste disposal in a complicated tedious way, therefore, the quality of the product still remains unimproved.
As for the chip array capacitor for high voltage application, the above mentioned two defects become minor problems to be worried. But a granulated surface resulted by the ceramic material brings the problems of high voltage discharging and leakage current caused by the affixed dirts. For a remedy, a long term study and investigation as to develop an improved dielectric material to overcome this embarrassment is necessary.
For these defects noticeable on the prior art, an improvement is seriously required.
The inventor has dedicated great efforts for years in studying and improving these defects and finally come up with a novel insulated structure of a chip array component and its fabrication method as provided in this invention to eliminate the defects mentioned above.